Arithmetic and logic unit

ABSTRACT

The controller system includes a control logic device and a controller arranged between a processor and the control logic device. The control logic device includes a stored initiation value for initiating a task activated by the control logic device, a device for making a comparison between the stored initiation value residing in the control logic device and an incrementally changing time value and a device for initiating the task when the stored initiation value therein corresponds to the incrementally changing time value. The controller advantageously includes a device for making a comparison of the new initiation value transferred from the processor, the stored initiation value and the time value with each other to obtain additional information; a device for transferring the new initiation value to the control logic device for storage as the stored initiation value after the comparison in the controller and a device for transmitting the additional information to the control logic device according to results of the comparison in the controller.

BACKGROUND OF THE INVENTION

The invention relates to an arithmetic and logic unit, in particularbelonging to a controller for internal combustion engine fuel injectionsystems and/or internal combustion engine ignition systems, having aprocessor and a control logic device, wherein a control device acting asan interface and carrying out specific processor tasks in order torelieve the load on the processor is connected between the processor andthe control logic device.

Arithmetic and logic units of the type mentioned initially are known.They are used, for example, for carrying out control tasks. In the caseof extensive control tasks, constrained addressing conditions andoverloading of the processor can occur, which lead to it not beingpossible to carry out the data processing in an available time interval.Changes which occur during the calculation of data and would lead todata changes are possibly no longer considered at the correct time ifthe processor is overloaded.

A device of the type mentioned initially is disclosed in German Patent27 32 781. This device has a microprocessor which is relieved of theload of determining specific signals, so that it can carry out its othertasks better.

SUMMARY OF THE INVENTION

The arithmetic and logic unit according to the invention has theadvantage that a controller is connected between the processor and thecontrol logic device, which controller acts as an interface and carriesout specific processor tasks in order to relieve the load on theprocessor. To this end, it is provided that information is transmittedbetween the processor and the control logic device in relation to whichthe controller generates additional information to which the controllogic device reacts. In the course of this application, "information" isto be understood to be electronic data information comprising addressesand/or data (datum). According to the above explanations, the processorthus carries out only part of the work; the other part of the work iscarried out by the controller. If data which are not changed by thecontroller are transmitted from the processor to the control logicdevice, then this area acts in a conventional manner, that is it appearsas if the processor is connected directly to the control logic device.In addition, however, the circumstance can arise in which the controllerproduces additional signals/information which are transmitted to thecontrol logic device via an internal bus, in particular an internalcontrol bus (ISB). In consequence, the processor is relieved of the loadsince it does not carry out the entire task. As has already beenmentioned above, it is additionally or alternatively also possible forinformation to be transmitted between the processor and the controllogic device, which information passes through the controller, beingchanged. In particular, data which are changed while passing through thecontroller are transmitted from the processor to the control logicdevice, the changed data passing from the controller to the controllogic device via an internal bus, in particular an internal data bus(IDB). Alternatively or additionally it is possible for information tobe transmitted between the processor and the control logic device topass through the controller which tests the information for specificcriteria and, if the criteria are not satisfied, refuses to pass theinformation on to the control logic device. The controller thus carriesout monitoring tasks which do not need to be carried out by theprocessor, and this leads to relief of the processor load. It isprovided in particular that data which are to be transmitted from theprocessor to the control logic device pass through the controller whichtests them for consistency and refuses to pass the data on to thecontrol logic device as a function of the test result. If the data areconsistent, that say the criteria applicable to the relevant case aresatisfied, then the data from the processor are transmitted to thecontrol logic device.

If specific conditions are not satisfied, then the component whichcarries out the check is not the processor but the controller, theprocessor admittedly finding out the generated data which, however, donot pass to the control logic device because of the blocking controller.The controller is preferably virtually "invisible" for the processor,that say the processor processes, for example, a control task and emitsdata to the control logic device which data, however, initially pass tothe controller and are possibly changed there. The controller thenpasses the possibly changed data on to the control logic device. Thework which is carried out by the actions of the controller thereforeneed not be carried out by the processor, so that it is relieved ofload.

In addition or alternatively, external information, for example externalinformation from the control process, is passed to the controller, whichinformation can initiate communication between the controller andcontrol logic device independently of the processor. For example,process parameters are not fed to the processor but to the controller,so that the processor is relieved of load. The controller autonomouslyprocesses these parameters or changes in the parameters interacting withthe control logic device without the processor "noticing" this.

In particular, the external information can be based on the occurrenceof an external event, data communication between the controller and thecontrol logic device taking place on the basis of the occurrence of theevent, which data communication--as stated--does not lead to theinvolvement of the processor.

BRIEF DESCRIPTION OF THE DRAWING

The objects, features and advantages of the invention will now beillustrated in more detail with the aid of the following description ofthe preferred embodiments, with reference to the accompanying figures inwhich:

FIG. 1 is a block diagram of an arithmetic and logic unit,

FIG. 2 shows an illustration of the problems of initial value changes

FIG. 3 shows an illustration corresponding to FIG. 2,

FIG. 4 is a block diagram and

FIG. 5 is a further block diagram.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention relates to an arithmetic and logic unit which has aprocessor and a control logic device, there being an "additional unit"in the microprocessor-controlled system, namely a controller, which isconnected as an interface between the processor and the control logicdevice and carries out tasks which have been offloaded from theprocessor. The interconnection of the controller and the control logicdevice is called a "controller system" in the following text.

According to FIG. 1, the controller system CS is controlled from theprocessor P by three line types. An address bus AB leads from theprocessor P to the controller system CS. A control bus SB furthermoreleads from the processor P to the controller system CS. Furthermore, ahold line HL is provided which leads from the controller system CS tothe processor P and is used to stop the processor P when the controllersystem CS is operating relatively slowly. If the action has beenprocessed in the controller system CS, then the processor P is requestedvia the hold line HL to feed information to the controller system CSonce again. Finally, the processor P is connected to the controllersystem CS via a bidirectional data bus DB.

The controller system CS comprises a controller C and a control logicdevice S. The controller C and the control logic device S are connectedto one another by means of an internal control bus ISB and by means of abidirectional internal data bus IDB and a bidirectional address bus IAB.

The processor P communicates with the controller system CS using eithera READ instruction or a WRITE instruction or a READMODIFYWRITEinstruction. In the READ mode, the processor P passes an address to theaddress bus AB and signals the READ instruction via the control bus SB.The controller C sets a HOLD signal in order to stop the processor P.This action can also be suppressed if the controller C reports to theprocessor P on the basis of the selected address that the controller Ccan carry out the desired READ action sufficiently fast, the controllerC is in principle fast enough, or if it can be seen from the addressthat the controller C has not been addressed. The controller C uses thereceived address to address the desired register, which can be locatedeither in the controller C or in the control logic device S. Thecontroller C transfers the data from the register via the data bus DB tothe processor P. After the data transfer has taken place, the HOLDsignal is withdrawn in order to allow the processor P to continue itswork.

In the WRITE mode, the processor P passes an address to the address busAB and signals the WRITE instruction via the control bus SB. At the sametime, the processor P passes the data to the data bus DB. The controllerC uses the received address to address the desired register, andtransfers the data from the data bus DB to this register, which can belocated in the controller C or in the control logic device S.

In the READMODIFYWRITE mode, the processor P passes an address to theaddress bus AB and signals the READ instruction via the control bus SB.At the same time, the controller C uses the received address to addressthe desired register, which, once again, can be located either in thecontroller C or in the control logic device, and transfers the data fromthe register to the processor P via the data bus DB. The processor Pprocesses the data, thus received, from the data bus DB. The processor Psignals the WRITE instruction via the control bus SB. At the same time,the processor P passes the newly processed data to the data bus DB. Thecontroller C uses the received address to address the desired registerand transfers the data from the data bus DB to this register.

According to another exemplary embodiment, it is also possible toprovide intermediate steps. The addressing of the control logic device Sis always an address specified by the processor P, it being possible forthis to be done however, via a plurality of steps and via a plurality ofbuffer-storage operations of a partial address in an address-supplementregister.

The invention provides that

a) data pass from the processor P to the control logic device S inunchanged form, additional signals being generated on the internalcontrol bus ISB, however, to which the control logic device S reacts,

b) the contents of the data are changed, that is corrected data aretransmitted from the controller C to the control logic device S via theinternal data bus IDB,

c) the data from the processor P are tested for consistency by thecontroller C, and passing said data on to the control logic device S ispossibly refused,

d) external events which are passed to the controller C can initiatedata communication between the controller C and the control logic deviceS independently of the processor P.

An exemplary embodiment of case a now follows. The following option foruse of the arithmetic and logic unit according to the invention will bedescribed first. This can be used for example, for carrying out tasks incontrollers of internal combustion engines. With the aid of thearithmetic and logic unit according to the invention, it is possible tocarry out driving of, assistance to and simplification of electroniccircuits for motor vehicle injection control systems and/or motorvehicle ignition control systems. Furthermore, the subject-matter of theinvention is suitable, in a simple manner, for the testing of electroniccircuits.

In the case of the cited injection system and ignition system tasks, itis necessary to compare a predetermined value (called the initial valueor initiation value) with a timer value which is changed incrementally.In the specific case of a motor vehicle controller, the system reactionis made dependent on the angular position of the cam shaft. The angularposition of the cam shaft, which changes in use, represents the timervalue. The following text is intended to describe the start and end ofan injection process. The movement direction of the angle, that is theangular position of the cam shaft, takes place in only one direction,that is the angular value can always only increase and the value rangeis repeated cyclically. When 359° is passed through, the angle isincremented to 360°, the angular value assigned to the angle jumpingback to the value 0°. Because of the cyclic nature, a description of arelatively large angular value and of a relatively small angular valuemeans the same as the terms "later" and "earlier". An injection processcan thus be started at 350° and ended at 20°, the initial value being"larger" than the final value of the injection action. An importantprecondition for use of the digital preset of a cyclic angle (timervalue or angular clock=angular position of the cam shaft) is theincremental change in the value. This means that, in the event of anychange, the angular clock value must assume all the values located inbetween in a rising sequence.

An action of the control unit must be carried out when a predetermined,stored "initiation value" corresponds with the value of the angularclock (angular position of the cam shaft). However, it must be notedthat a change in the initiation value must not take place at the sametime as the change in the angular clock. Reference is made to FIG. 2 inthis context. In this figure, the meanings are: a=previous initiatingvalue (initiation has already taken place), b=new initiating value,c=current actual value and d=incremental event (timer). If it isintended to reduce the initiation value from, for example, 25° to 24° inorder to advance the start of the injection process without using acontroller C, the angular clock value must not be increased from 24° to25° at the same time. In such a case, the arithmetic and logic unit inthe control system S cannot detect correspondence of the values and theintended action of "injection" does not occur.

For the same reason, a change in the initiation value cannot be carriedout without knowledge of the current angular clock status (cf. FIG. 3).In FIG. 3, the meanings are: e=new initiating value (there is no longeridentity), f=previous initiating value, g=current actual value andh=incremental event (timer). If it is intended to reduce the initiationvalue from, for example, 25° to 20° in order to advance the start of theinjection process without using a controller C, the angular clock valuemust not at the same time be in the range from 21° to 24°, since novalue correspondence can be detected in this case either, so that theangular clock value is "jumped over".

In order to solve the above problems in changing the initial value in afuel injection system of an internal combustion engine, the controller Cmust know the current actual values of the "angular clock" (angularposition of the cam shaft). This is preferably done either by theangular clock being generated in the controller C or by correspondinginformation on the state of the angular clock being fed to an input ofthe controller C. The processor P presets an initiation value, that isthe initial value for the start of the injection process. The processorP writes this new initiation value into the control logic device S asthe initial value. The controller C uses the address to detect the factthat this is an initiation value, and writes this new initiation valueinto a buffer store. At the same time, the controller C uses theunchanged address to read the old initiation value, which was validuntil now. The difference between the data of the new initiation value,the old initiation value and the currently present position of theangular clock is used to determine whether this is the case in FIG. 2 orthe case in FIG. 3, or neither of the two cases. This additionalinformation is sent together with the buffer-stored new initiation valuefrom the controller C to the control system S, so that the latter caninitiate an injection process (case 2, FIG. 3) or sets an identifierthat the next initiation must be ignored since it has already takenplace (case 1, FIG. 2). From the above argument, it becomes clear thatdata from the processor P are transmitted to the control logic device Sin an admittedly unchanged form, additional signals being generated,however, to which the control logic device reacts.

The following table shows the respective reaction of the arithmetic andlogic unit for the various cases.

    ______________________________________                                        Comparisons:                                                                  New.sub.-- initial value                                                                 New.sub.-- initial value                                                                   Old.sub.-- initial value                                                                   Re-                                      ? Old.sub.-- initial value                                                               ? Angular clock                                                                            ? Angular clock                                                                            action:                                  ______________________________________                                        =          any          any          Case 0                                   >          =            <            Case 3                                   >          >            =            Case 1                                   >          >            >            Case 3                                   >          >            <            Case 1                                   >          <            any          Case 3                                   <          =            >            Case 2                                   <          >            any          Case 3                                   <          <            =            Case 3                                   <          <            >            Case 2                                   <          <            <            Case 3                                   ______________________________________                                         Case 0: No reaction, new value does not need to be transferred to the         control logic device.                                                         Case 1: In addition to the new value, the control logic device receives       the information that the initiation has already taken place, in order to      suppress second initiation, cf. FIG. 2.                                       Case 2: As well as the new value, the control logic device receives the       instruction to initiate, cf. FIG. 3.                                          Case 3: No additional reaction while the new value is being transferred t     the control logic device.                                                

Using the example, mentioned above, of the fuel injection system of aninternal combustion engine, it is intended to describe case b, in whichthe arithmetic and logic unit according to the invention changes thecontext of data, that is the corrected data are transmitted from thecontroller C to the control logic device S via the internal data busIDB. The same preconditions apply as those explained in the example forcase a. It is now assumed that the processor P writes a new initiationvalue into the control logic device S. The controller C uses the addressto detect the fact that this is an initiation value, and writes this newinitiation value into a buffer store. At the same time, the controller Cuses the unchanged address to read the preceding, old initiation valueinto a second buffer store. The difference between the data is used todetermine whether the new initiation value is larger than or smallerthan the old initiation value. Instead of a single writing process intothe control logic S, the old initiation value is matched by incrementalsteps to the new initiation value, in that a corresponding number ofsuccessively following writing processes are generated from thecontroller C to the control logic device S, whose data in each caseapproach the desired new initiation value by the value 1.

In order to carry out a relative data change, that is the statement ofthe change to an item of data, the processor P writes the desired changein the initiation value into the control logic device S and identifiesthis value as a relative value, either by using a modified address or bysetting a fixed bit in the data item (the data). The controller C storesthis new relative initiation value in a buffer store. At the same time,the controller C uses the unchanged address, or the address which hasbeen modified back, to read the old initiation value into a secondbuffer store. The sum of the old initiation value and the new initiationvalue is determined and is written back using the unchanged address, orthe address which has been modified back, to the control logic device S.By transmitting the relative value "-2", the processor P thus initiatesa reduction in the initiation value by two units, without any knowledgeof the current initiation value.

This process can also be implemented by the processor P which, however,requires a number of program steps for this purpose and thereforerequires a certain amount of time. However, this covers the possibilitythat conditions (for example the position of the angular clock) canchange during the computation time, as a result of which either thereaction becomes inaccurate or the program can become large andcomplicated in order to cover all the possible cases, but in any casethe processing can become time-intensive.

Reference is made to FIG. 4 with respect to the possibility ofprocessing relative changes of data. The meanings in this case arei=write the ACTUAL value and k=write the NEW value. If a conversion fromrelative data to absolute data is allowed, then the previous registervalue OLD is read and is added to a currently applicable register valueACTUAL. This addition is carried out in the adder ADD. It is alsopossible subsequently to enter the controller sequence at this point bymeans of status bits which are read in parallel. The sum NEW formed isstored and is passed back in the next step to the control logic deviceS, via the internal data bus IDB, as an absolute data item with a writecommand.

If conversion from relative data to absolute data is not allowed,then--according to FIG. 4--a write instruction is passed with the dataACTUAL to the control logic device S.

FIG. 5 describes register changes, that is, for example, an initiationvalue change in the fuel injection process. In the case of the change ina register value, the controller C tests its reaction using a maximum offour questions: firstly, it uses the register address to decide whetherthis is an initiation value register. In this case, the previous initialvalue OLD is read and is compared on the one hand with the new value NEWand on the other hand with the current ACTUAL value (ACTUAL). Thedifference between ACTUAL and NEW is formed as a last comparison. Theresults of these three comparisons are used to determine whether, forexample, "jumping over" in accordance with FIGS. 2 and 3 has occurred.The new data NEW are sent in parallel to the control logic device S. Thereaction to this is left to the control logic device S. The meanings inFIG. 5 are: m=write other values, n=write NEW value, o=write ACTUALvalue, p=switch and q=result memory (for example shift register).

An exemplary embodiment of case c is now considered, that is for testingthe data for consistency. In order to refuse inconsistent data, thecontroller C must know the tolerance band. The knowledge of thistolerance band is assumed. The processor P writes a new initiation valueinto the control logic device S. The controller C uses the address todetect the fact that this is an initiation value, and writes this valueas the new initiation value into a buffer store. At the same time, thecontroller C uses the unchanged address to read the old initiation valueinto a second buffer store. The difference between the data is used todetermine whether the new initiation value is larger than or smallerthan the old initiation value. The controller C checks whether the newinitiation value is in the defined tolerance band and/or whether thedifference between the new initiation value and the old initiation valueis in a defined, acceptable band. The new initiation value is not passedon from the controller C to the control logic device S unless theseconditions are met.

In the case of control of the angular clock, the controller C receivesan "angular clock" register and reports any change in the angular clockexplicitly to the control logic device S. The processor P initiates aprocess of "incrementation of the angular clock", which increases thecontents of the "angular clock" register by one increment. After thisincrease, the value of the "angular clock" register is sent via theinternal data bus IDB to the control logic device S, while a specificcombination of data on the internal address bus IAB and/or on theinternal control bus ISB designates this process. The control logicdevice S can then compare the value of the angular clock with its owndata, and initiate the corresponding reactions.

The following example is intended to illustrate case d, namely externalevents which are passed to the controller C, it being possible toinitiate data communication between the controller C and the controllogic device S independently of the processor P. In the case ofautomatic control of the angular clock, the controller C receives an"angular clock" register and reports any change in the angular clockexplicitly to the control logic device S. An external (clock) eventinitiates a process of "incrementation of the angular clock", whichincreases the contents of the "angular clock" register by one increment.After this increase, the value of the "angular clock" register is sentvia the internal data bus IDB to the control logic device S, while aspecific combination of data on the internal address bus IAB and/or onthe internal control bus ISB designates this process. The control logicdevice S can then compare the value of the angular clock with its owndata, and initiate the corresponding reactions.

In a further example of the test case of the control logic device, thecontroller receives a data field (ReadOnlyMemory ROM) which contains aprogram and comprises statements on the required behavior of the controllogic device. An external (test) event or the processor P initiates a"start test program" process; the controller C processes the programwhich is in the data field and in each case compares the requiredbehavior, which can be seen on the internal busses IAB, IDB and ISB, ofthe control logic device with the stored data. In the event of anunpredicted reaction, either an error bit is set in a status register ofthe controller C or the test program is terminated, or the defectivebehavior is recorded. The processor P can thus test the correct behaviorof the control logic device S without any activity itself. The testprogram can be a program which tests control logic devices, of whichthere are a number and which differ only by the address, either inparallel or successively by calling the test program a plurality oftimes. In the first case, part of the address on the internal addressbus IAB is designated by the controller C, via the internal control busISB, as being ineffective (alternative: the control logic devices reactidentically to two addresses, the second address being the same for allthe control logic devices), in the second case, the address in the testprogram is supplemented by a data item which is stored in the controllerC to form the actual control logic device address for the internaladdress bus IAB. It is also conceivable to implement both casesalternatively.

The following text is intended to describe an arithmetic and logic unitwhich carries out the ignition system control in an internal combustionengine. In the case of the ignition system control, it is assumed thatan ignition process starts by switching an ignition transistor at theangle αb and ends by switching off this ignition transistor, and thegeneration of an ignition spark, at an angle αe.

The controller C which is used has a plurality of, preferably eight,identical control logic devices which are controlled. Each of thesecontrol logic devices contains four registers, two of which are used as"start registers". The controller C additionally contains eight of itsown registers, including two angular clocks, one of which is presetexternally and the other is produced internally.

The above-mentioned angles αb and αe are present in two start registersof the control logic device S. The control logic device S further has astatus register, in which the following statements are located:

whether an ignition control process is intended to be made,

which of the two angular clocks is intended to be used,

whether it is intended to carry out an ignition duration check,

whether it is intended to carry out a check of the initial valuechanges.

The controller C contains two statements for controlling the ignitiondurations in the "minimum time" and "maximum time" registers.

The controller C has implemented the distinguishing of the cases forinitial value changing via two lines of the internal control bus ISB.For every angular clock change, it sends the new angular clock value atan IAB angular clock address via the internal data bus IDB. The angularclock and start register cannot be changed simultaneously from the viewpoint of the control logic device S by the internal data bus IDB, intowhich inputs can be made at only one end. WRITE data from the processorP to a start register are intercepted by the controller C. Thecontroller C reads both the previous value of the start register and thecontents of the status register of the relevant control logic device. Ifthe check of the initial value changes is impeded by this, thecontroller C writes the WRITE data to the start register immediately.Otherwise, it uses the values read and the selected angular clock todetermine the reaction of the control logic device S, and transmits thisstatement together with the WRITE data of the start register S inaccordance with case a). The initiation of an ignition process isprepared by the detection of the start register 1=angular clock byswitching on the ignition transistor and is ended by the detection ofthe start register 2=angular clock by switching off the ignitiontransistor and producing the ignition spark. If a check of the ignitiondurations is required by the control logic device status register, oncean ignition process has been initiated by the detection of the startregister 1=angular clock by switching on the ignition transistor thecontroller C is requested by the control logic device S, by means of aline of the internal status bus ISB, to output the value "minimum time"to the internal data bus IDB. This value is stored in an internal timerin the control logic device and is decremented to zero using a countingclock which is transmitted via the internal control bus ISB. As long asthis timer is not equal to zero, the ignition transistor is not switchedoff, in order to ensure an ignition process, even if detection of the"start register 2"=angular clock occurs. If this detection occurs, theignition transistor is switched off and the ignition spark is thusproduced as soon as the timer reaches the value zero. If this detectiondoes not occur, once the timer has elapsed, the control logic device Srequests the controller C, via a further line of the internal status busISB, to output the value "maximum time" to the internal data bus IDB.This value is likewise stored in the timer and is decremented to zero.Detection of "start register 2"=angular clock switches the ignitiontransistor off in order to produce the ignition spark, and stops thetimer. The sum of minimum time+maximum time-timer value can becalculated by the processor and thus, if necessary, the processorreceives the precise duration of the ignition transistor activity. Ifthe timer reaches the value zero, the ignition transistor is alwaysswitched off, for protection against overloading.

In the case of the implementation of an injection control system, theprocedure is as follows:

An injection process starts at the angle αb by switching on an injectionvalve, and ends after an injection time t, by switching this valve off.The angle and injection time t are also located in both start registers.The following statements are located in the status register of thecontrol logic device S:

whether an injection control process is intended to be made,

which of the two angular clocks is intended to be used,

whether it is intended to carry out a check of the initial valuechanges.

The controller C has implemented the distinguishing of the cases forinitial value changing via two lines of the internal control bus ISB.For every angular clock change, it sends the new angular clock value atan IAB angular clock address via the internal data bus IDB. The angularclock and start register cannot be changed simultaneously from the viewpoint of the control logic device S by the internal data bus IDB, intowhich inputs can be made at only one end. WRITE data from the processorP to a start register are intercepted by the controller C. Thecontroller C reads both the previous value of the start register and thecontents of the status register of the relevant control logic device S.If this prevents the check of the initial value changes or theaddressing of the start register 2 during an injection control processis identified, the controller C writes the WRITE data into the startregister immediately. Otherwise, it uses the values read and theselected angular clock to determine the reaction of the control logicdevice S, and transmits this statement together with the WRITE data ofthe start register S. The initiation of an injection process is startedby the detection of start register 1=angular clock, by the control logicdevice S copying the value of the start register 2 (that is theinjection time t) into an internal timer in the control logic devicewhich is decremented using a counting clock which is sent via theinternal control bus ISB. As long as the timer contains a value which isnot equal to zero, the injection valve is switched on or remainsswitched on. If a repeated initiation of an injection process isdetected by the detection of start register 1=angular clock, while thepreceding injection process is still active, the value of the startregister 2 is once again copied into the timer and the valve remainsswitched on. In this way, a continuous injection process can beimplemented. If the timer is changed during an injection process by theprocessor P or the controller C by means of a WRITE instruction, this isused to extend or shorten (down to immediate termination if a zero iswritten in) the injection process. If the timer is changed outside aninjection process by the processor P or the controller C by means of aWRITE instruction from zero to a value which is not equal to zero, thisis used for subsequent injection of fuel in the event of large loadchanges (for example full accelerator suddenly applied) by switching theinjection valve on once again.

I claim:
 1. A controller system comprising a control logic device and acontroller connected between a processor and the control logicdevice,wherein said control logic device includes a stored initiationvalue for initiating a task to be activated by the control logic device,means for making a comparison between the stored initiation valueresiding in the control logic device and an incrementally changing timevalue and means for initiating the task when the stored initiation valuetherein corresponds to the incrementally changing time value; and thecontroller includes means for making a comparison of a new initiationvalue transferred thereto from the processor, the stored initiationvalue and the time value with each other to obtain additionalinformation, means for transferring the new initiation value to thecontrol logic device for storage as the stored initiation value afterthe comparison in the controller and means for transmitting saidadditional information to the control logic device according to resultsof the comparison in the controller.
 2. The controller system as definedin claim 1, wherein the control logic device includes means foractivating the control logic device and initiating the task immediatelywhen the additional information is received therein.
 3. The controllersystem as defined in claim 1, wherein the control logic device includesmeans for not activating the control logic device and not initiating thetask when the additional information is received therein.
 4. Thecontroller system as defined in claim 1, further comprising means fortransferring informational data regarding the new initiating value fromthe processor to the controller, and wherein said informational datacomprises the stored initiating value.
 5. The controller system asdefined in claim 1, further comprising means for transferringinformational data regarding the new initiating value from the processorto the controller, and wherein said informational data comprises arelative value and said controller includes means for determining a newinitiation value by analysis of the relative value and the storedinitiation value.
 6. The controller system as defined in claim 1,wherein the controller includes means for testing whether said newinitiating value is within a predetermined tolerance range during thecomparison in the controller and means for preventing storage of the newinitiating value in the control logic device as the stored initiatingvalue when the new initiating value is outside the predeterminedtolerance range.